Allen-Bradley 1770-M11 User Manual download pdf (Page 25)

SLC 500™ Chassis–Based Processors 25

Publication 1747-2.39

Instruction Execution Times

Execution Time Example - Bit Instruction Using an Indirect

Address

To calculate the execution time of an XIC at B3/[N7:0] using an

SLC 5/03 processor add the following:

Execution Time for Bit–Level Indirect Address + Instruction Execution

Time =10.20 + 96.70 = 106.90

Specifications

The following table summarizes the detailed specifications for

the SLC 500 processor family:

Instruction

Execution Time (

SLC 5/03

SLC 5/04

SLC 5/05

XIC 10.20 8.72

XIO 14.65 12.76

OTU 6.30 5.45

OTL 9.35 5.40

OTE 6.25 5.50

OSR 10.50 8.10

Specification

SLC 5/01 SLC 5/02 SLC 5/03 SLC 5/04 SLC 5/05

1747–L511

1747–L514

1747–L524

1747–L531

1747–L532

1747–L541

1747–L542

1747–L543

1747–L551

1747–L552

1747–L553

Memory Size

(words)

1K (1747–L511)

4K (1747–L514)

8K (1747–L531)

16K (1747–L532)

16K (1747–L541)

32K (1747–L542)

64K (1747–L543)

16K (1747–L551)

32K (1747–L552)

64K (1747–L553)

Max. I/O Capacity 3940 Discrete 4096 Discrete 4096 Discrete 4096 Discrete 4096 Discrete

Max. Local

Chassis/Slots

3/30 3/30 3/30 3/30 3/30

Programming

•RSLogix 500 (V1.00 or later),

SLC–500 A.I. Series

•APS Programming Software

•HHT

1747–L531:

•RSLogix 500

(V1.26.03 or later)

•SLC 500 A.I. Series

(V8.15 or later)

1747–L532:

•RSLogix 500

(V1.24.04 or later)

•SLC 500 A.I. Series

(V8.10 or later)

•APS (V6.0 or later)

•RSLogix 500

(V1.24.04 or later)

•SLC 500 A.I.

Series

(V8.10 or later)

•APS (

V6.0 or later)

•RSLogix 500

(V2.10 or later)

Programming

Instructions

52 71

99 99

Typical Scan

Time

8 ms/K 4.8 ms/K

1 ms/K

0.9 ms/K 0.9 ms/K

Bit Execution

(XIC)

s2.4

0.44

0.37

s0.37

a.The scan times are typical for a 1K ladder logic program consisting of simple ladder logic and communication servicing. Actual scan times

depend onyour program size, instructions used and the communication protocol.

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Allen-Bradley 1770-M11 User Manual Page 25

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