22 SLC 500™ Chassis–Based Processors
Publication 1747-2.39
Interrupt Routine Instructions
Indirect Addressing
The following sections describe how indirect addressing affects
the execution time of instructions in the SLC 5/03 OS302, SLC 5/
04 OS401, and SLC 5/05 processors. The timing for an indirect
address is affected by:
• the form of the indirect address
• if the indirect address is a source or destination parameter
• whether indirect addressing is used in either a COP, FLL,
FFL/FFU, LFL/LFU, BSR, BSL, or MVM instruction
• whether indirect addressing is used in either an XIC, XIO,
OTU, OTL, OTE, or OSR instruction
For the address forms in the table on the next page, you can
substitute the following file types:
Instruction Mnemonic
and Name
Execution Times (µs)
Function -
Output Instructions
SLC 5/01 SLC 5/02 SLC 5/03
SLC 5/04
SLC 5/05
STD Selectable Timed
Disable
—9 4 3.56
Associated with the Selectable Timed
Interrupt function. STD and STE are used to
prevent an STI from occurring during a portion
of the program; STS initiates an STI.
STE Selectable Timed
Enable
—9 5 5.0
STS Selectable Timed
Start
— 72 58 44.38
IIE I/O Interrupt Enable — 42 16 10.44
The IIE, IID and RPI instructions are used with
specialty I/O modules capable of generating
an I/O interrupt.
IID I/O Interrupt Disable — 39 6 5.81
RPI Reset Pending I/O
Interrupt
— 240
78 + 60 per
added slot
91 + 56 per
added slot
REF I/O Refresh — 240 240 200
When conditions preceding it in the rung are
true, the REF instruction interrupts the
program scan to execute the I/O scan (write
outputs-service comms-read inputs). The
program scan then resumes.
INT Interrupt
Subroutine
— 0 0.25 0.18
Associated with STI interrupts and I/O event-
driven interrupts.
For an Integer (N) For a String (ST)
Input (I) Control (R)
Output (O) Counter (C)
Bit (B) Timer (T)
Floating Point (F)
ASCII (A)
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