18 SLC 500™ Chassis–Based Processors
Publication 1747-2.39
Data Handling Instructions
Instruction
Mnemonic
and Name
Execution Times (µs) Floating Point
(µs)
b
c
Function -
Output Instructions
SLC 5/01 SLC 5/02 SLC 5/03
SLC 5/04
SLC 5/05
TOD Convert
to BCD
200 122 38 34.06
When rung conditions are true, the TOD instruction converts
the source value to BCD and stores it in the math register or
the destination.
FRD Convert
from BCD
223 136 31 23.88
When rung conditions are true, the FRD instruction converts a
BCD value in the math register or the source to an integer and
stores it in the destination.
RAD Degrees
to Radians
a
——
d
/ 31.80
d
/ 24.65
When rung conditions are true, RAD converts degrees (source)
to radians and stores the result in the destination.
DEG Radians
to Degrees
a
——
d
/ 32.80
d
/ 24.70
When rung conditions are true, DEG converts radians (source)
to degrees and stores the result in the destination.
DCD Decode 80 50 10 8.88
When rung conditions are true, the DCD instruction decodes
4–bit value (0 to 16), turning on the corresponding bit in 16–bit
destination.
COP File Copy
45 + 21 per
word
29 + 13 per
word
30 + 2.20 per
word
20.2 + 2.0
per word
When rung conditions are true, the COP instruction copies a
user–defined source file to the destination file.
FLL File Fill
37 + 14 per
word
25 + 8 per
word
28 + 2 per
word
21.9 + 2.5
per word
When rung conditions are true, the FLL instruction loads a
source value into specified elements in a user–defined file.
MOV Move 20 14 1.25 / 12.19 1.12 / 11.44
When rung conditions are true, the MOV instruction moves a
copy of the source to the destination.
MVM Masked
Move
115 71 19 17.40
When rung conditions are true, the MVM instruction moves a
copy of the source through a mask to the destination.
AND And 87 55 1.70 1.5
When rung conditions are true, sources A and B of the AND
instruction are ANDed and stored in the destination.
OR Inclusive
Or
87 55 1.70 1.5
When rung conditions are true, sources A and B of the OR
instruction are ORed bit by bit and stored in the destination.
XOR Exclusive
Or
87 55 1.70 1.5
When rung conditions are true, sources A and B of the XOR
instruction are Exclusive ORed and stored in destination.
NOT Not 66 42 1.70 1.5
When rung conditions are true, the source of the NOT
instruction is NOTed bit by bit and stored in the destination.
FFL Load — 150 58 40.75 First In First Out (FIFO). The FFL instruction loads a word into
a FIFO stack on successive false–to–true transitions. The FFU
unloads a word from the stack on successive false–to–true
transitions. The first word loaded is the first to be unloaded.
FFU Unload —
150 + 11 per
word
79 + 2.20 per
word
60 + 2 per
word
LFL Load — 150 58 40.70 Last In First Out (LIFO). The LFL instruction loads a word into a
LIFO stack on successive false–to–true transitions. The LFU
unloads a word from the stack on successive false–to–true
transitions. The last word loaded is the first to be unloaded.
LFU Unload — 180 66 34.70
a.Applies to SLC 5/03 OS302 and SLC 5/04 OS401 processors.
b.Floating point times do not apply to SLC 5/03 OS300 processors.
c.When only one Execution Time is listed for an instruction, Floating Point does not apply.
d.The execution times assum floating point data. If signed integer data is used, add 15 microseconds per instruction execution time.
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